This disclosure relates to an equalizer and a semiconductor memory device including the same, and more particularly, to an equalizer having a reduced layout area and a semiconductor memory device including the same.
A plurality of tri-state buffers for sequentially outputting data are used at an internal or external node of a semiconductor memory device, such as DRAM or flash memory. The plurality of tri-state buffers may have a high impedance state during an operation. As the plurality of tri-state buffers are in a high impedance state, when an output node floats, a semiconductor memory device may operate unstably. Moreover, when a semiconductor memory device operates at high speed, intersymbol interference (ISI) may occur in an output signal of a tri-state buffer.